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ds07-13730-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90340 series mb90f342/c(s), mb90f343/c(s), mb90f345/c(s), mb90f346/c(s), mb90f347/c(s), mb90f349/c(s), mb90341/c(s), mb90342/c(s), mb90346/c(s), mb90347/c(s), mb90348/c(s), mb90349/c(s), mb90v340(s) n description the mb90340-series with up to 2 full-can* interfaces and flash rom is especially designed for automotive and industrial applications. its main feature are the on-board can interfaces, which conform to v2.0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full can approach. with the new 0.35 m m cmos technology, fujitsu now offers on-chip flash-rom program memory up to 512 kbytes. an internal voltage booster removes the necessity for a second programming voltage. an on board voltage regulator provides 3 v to the internal mcu core. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 mhz clock. the unit features an 8 channel output compare unit and 8 channel input capture unit with 2 separate 16-bit free running timers. 4 uarts constitute additional functionality for communication purposes. * : controller area network (can) - license of robert bosch gmbh note : f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n pac k ag e s 100-pin plastic qfp 100-pin plastic lqfp (fpt-100p-m06) (fpt-100p-m05)
mb90340 series 2 n features clock ? built-in pll clock frequency multiplication circuit ? selection of machine clocks (pll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 mhz oscillation clock, 4 mhz to 24 mhz). ? operation by sub-clock (up to 50 khz : 100 khz oscillation clock divided two) is allowed. (devices without s- suffix only) ? minimum execution time of instruction : 42 ns (when operating with 4-mhz oscillation clock, and 6-time multi- plied pll clock). 16 mbyte cpu memory space ? 24-bit internal addressing instruction system best suited to controller ? wide choice of data types (bit, byte, word, and long word) ? wide choice of addressing modes(23 types) ? enhanced multiply-divide instructions and reti instructions ? enhanced high-precision computing with 32-bit accumulator instruction system compatible with high-level language (c language) and multitask ? employing system stack pointer ? enhanced various pointer indirect instructions ? barrel shift instructions increased processing speed ? 4-byte instruction queue powerful interrupt function ? powerful 8-level, 34-condition interrupt feature ? up to 16 external interrupts are supported automatic data transfer function independent of cpu ? expanded intelligent i/o service function (ei 2 os) : up to 16 channels ? dma : up to 16 channels low power consumption (standby) mode ? sleep mode (a mode that halts cpu operating clock) ? time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only) ? watch mode (a mode that operates sub clock and clock timer only) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu blocking operation mode process ?cmos technology i/o port ? general-purpose input/output port (cmos output) - 80 ports (devices without s-suffix) - 82 ports (devices with s-suffix) timer ? time-base timer, clock timer, watchdog timer : 1 channel ? 8/16-bit ppg timer : 8-bit x 16 channels, or 16-bit x 8 channels ? 16-bit reload timer : 4 channels ? 16- bit input/output timer - 16-bit free run timer : 2 channel (frt0 : icu 0/1/2/3, ocu 0/1/2/3, frt1 : icu 4/5/6/7, ocu 4/5/6/7)
mb90340 series 3 - 16- bit input capture: (icu) : 8 channels - 16-bit output compare : (ocu) : 8 channels full-can interface : up to 2 channels ? compliant with ver2.0a and ver2.0b can specifications ? flexible message buffering (mailbox and fifo buffering can be mixed) ? can wake-up function uart (lin/sci) : up to 4 channels ? equipped with full-duplex double buffer ? clock-asynchronous or clock-synchronous serial transmission is available i 2 c interface* : up to 2 channels (devices with c-suffix only) ? up to 400 kbit/s transfer rate dtp/external interrupt : up to 16 channels, can wakeup : up to 2 channels ? module for activation of expanded intelligent i/o service (ei 2 os), dma, and generation of external interrupt. delay interrupt generator module ? generates interrupt request for task switching. 8/10-bit a/d converter : 16/24 channels ? resolution is selectable between 8-bit and 10-bit. ? activation by external trigger input is allowed. ? conversion time : 3 m s (at 24-mhz machine clock, including sampling time) program patch function ? address matching detection for 6 address pointers. internal voltage regulator ? supports 3 v mcu core, offering low emi and low power consumption figures programmable input levels ? automotive/cmos-schmitt (initial level is automotive in single chip mode) ? ttl level (initial level for external bus mode) rom security function ? protects the content of rom (mask rom device only) external bus interface clock monitor function * : i 2 c license : this product includes licensing of phillips i 2 c patents if used by the customer in an i 2 c system subject to the i 2 c standard specifications established by phillips.
mb90340 series 4 n product lineup (continued) part number parameter mb90f342/c(s),mb90f343/c(s)* 1 , mb90f345/c(s), mb90f346/c(s), mb90f347/c(s), mb90f349/c(s), mb90341/c(s)* 1 , mb90342/c(s)* 1 , mb90346/c(s) , mb90347/c(s), mb90348/c(s)* 1 , mb90349/c(s)* 1 mb90v340(s) cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz osc. pll 6) rom boot-block, flash memory 512 kbytes : mb90f345/c (s) 384 kbytes : mb90f343/c (s) 256 kbytes : mb90f342/c (s) , mb90f349/c (s) , mb90342/c (s) , mb90349/c (s) 128 kbytes : mb90f347/c (s) , mb90341/c (s) , mb90348/c (s) , mb90347/c (s) 64 kbytes : mb90f346/c (s) , mb90346/c (s) external ram 20 kbytes : mb90f343/c (s) , mb90f345/c (s) 16 kbytes : mb90f342/c (s) , mb90f349/c (s) , mb90341/c (s) , mb90342/c (s) , mb90348/c (s) , mb90349/c (s) 6 kbytes : mb90f347/c (s) , mb90347/c (s) 2 kbytes : mb90f346/c (s) , mb90346/c (s) 30 kbytes emulator-specific power supply *2 ? yes technology 0.35 m m cmos with on-chip voltage regulator for internal power supply + flash memory with on-chip charge pump for programming voltage 0.35 m m cmos with on-chip voltage regulator for internal power supply operating voltage range 3.5 v - 5.5 v : at normal operating (not using a/d converter) 4.0 v - 5.5 v : at using a/d converter/flash programming 4.5 v - 5.5 v : at using external bus 5 v 10 % temperature range - 40 c to + 105 c ? package qfp-100, lqfp-100 pga-299 uart 4 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbit/s) devices with c-suffix : 2ch devices without c-suffix : ? 2 channel a/d converter devices with c-suffix : 24ch devices without c-suffix : 16ch 24 input channels 10-bit or 8-bit resolution conversion time : min 3 m s include sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function 16-bit i/o timer (2 channels) signals an interrupt when overflowing supports timer clear when a match with output compare (channel 0, 4) operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock freq.) i/o timer 0 (clock input frck0) corresponds to icu 0/1/2/3, ocu 0/1/2/3 i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7
mb90340 series 5 (continued) part number parameter mb90f342/c(s),mb90f343/c(s)* 1 , mb90f345/c(s), mb90f346/c(s), mb90f347/c(s), mb90f349/c(s), mb90341/c(s)* 1 , mb90342/c(s)* 1 , mb90346/c(s) , mb90347/c(s), mb90348/c(s)* 1 , mb90349/c(s)* 1 mb90v340(s) 16-bit output compare (8 channels) signals an interrupt when 16-bit i/o timer match output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture (8 channels) rising edge, falling edge or rising & falling edge sensitive signals an interrupt upon external event 8/16-bit programmable pulse generator (8 channels) supports 8-bit and 16-bit operation modes sixteen 8-bit reload counters sixteen 8-bit reload registers for l pulse width sixteen 8-bit reload registers for h pulse width a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 m s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 2 channels : mb90f342/c (s) , mb90f343/c (s) , mb90f345/c (s) , mb90341/c (s) , mb90342/c (s) 1channel : mb90f346/c (s) , mb90f347/c (s) , mb90f349/c (s) , mb90346/c (s) , mb90347/c (s) , mb90348/c (s) , mb90349/c (s) 3 channels conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps external interrupt (16 channels) can be used rising edge, falling edge, starting up by h/l level input, external interrupt, expanded inteligent i/o services (ei 2 os) and dma d/a converter ? 2 channels up to100 khz subclock for low power operation devices with s-suffix : with subclock devices without s-suffix : without subclock i/o ports virtually all external pins can be used as general purpose i/o port all push-pull outputs bit-wise settable as input/output or peripheral signal settable in pin-wise of 8 as cmos schmitt trigger/ automotive inputs (default) ttl input level settable for external bus (32-pin only for external bus)
mb90340 series 6 (continued) *1 : the devices other than mb90f342/c (s) , mb90f345/c (s) , mb90f346/c (s) , mb90f347/c (s) , mb90f349/c (s) , mb90346/c (s) and mb90347/c (s) are under development. *2 : it is setting of jumper switch (tool v cc ) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. *3 : embedded algorithm is a trade mark of advanced micro devices inc. part number parameter mb90f342/c(s),mb90f343/c(s)* 1 , mb90f345/c(s), mb90f346/c(s), mb90f347/c(s), mb90f349/c(s), mb90341/c(s)* 1 , mb90342/c(s)* 1 , mb90346/c(s) , mb90347/c(s), mb90348/c(s)* 1 , mb90349/c(s)* 1 mb90v340(s) flash memory supports automatic programming, embedded algorithm tm*3 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block block protection with external programming voltage flash security feature for protecting the content of the flash (except for mb90f346/c (s) ) ? rom security protects the content of rom (mask rom device only) ?
mb90340 series 7 n pin assignments ? mb90v340(s) (continued) (top view) (fpt-100p-m06) * : mb90v340: x0a, x1a mb90v340s: p40, p41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 30 18 p75/an21/int5 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p56/an14/da00 p55/an13 p54/an12/tot3 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 qfp - 100 21 20 17 16 19 18 15 14 13 12 11 26 25 24 23 22 27 28 29 4 356 29 710 80 51 58 71 70 67 66 69 68 65 64 63 62 61 76 75 74 73 72 77 78 79 54 53 55 56 52 59 57 60 p57/an15/da01 p74/an20/int4 p73/an19/int3 p72/an18/int2 p60/an0/ppg0(1) p61/an1/ppg2(3) p62/an2/ppg4(5) p63/an3/ppg6(7) p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) vss p70/an16/int0 p71/an17/int1 avcc avrh avrl avss rst p31/rd/in5 p32/wrl/wr/rx2/int10r p33/wrh/tx2 p35/hak/out5
mb90340 series 8 (continued) (top view) (fpt-100p-m05) * : mb90v340 : x0a, x1a mb90v340s : p40, p41 75 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/an21/int5 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15/da01 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 lqfp - 100 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14/da00 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 58 59 55 56 57 54 53 52 51 12345678910111213141516 18 17 21 20 19 22 23 24 25 rst p31/rd/in5 p32/wrl/wr/rx2/int10r p33/wrh/tx2 p35/hak/out5
mb90340 series 9 ? mb90f342 (s) /mb90f343 (s) /mb90f345 (s) /mb90f346 (s) /mb90f347 (s) /mb90f349 (s) /mb90341 (s) /mb90342 (s) , mb90346 (s) /mb90347 (s) /mb90348 (s) /mb90349 (s) (continued) (top view) (fpt-100p-m06) * : mb90f342/f343/f345/f346/f347/f349/341/342/346/347/348/349 : x0a, x1a mb90f342s/f343s/f345s/f346s/f347s/f349s/341s/342s/346s/347s/348s/349s : p40,p41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/int5 p74/int4 p73/int3 p72/int2 p71/int1 p70/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/int7 p76/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p32/wrlx/wrx/int10r p34/hrq/out4 p56/an14 p55/an13 p54/an12/tot3 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47 p46 p45/frck1 p44/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a * p40/x0a * p37/clk/out7 p36/rdy/out6 qfp - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 rst p31/rd/in5 p33/wrh p35/hak/out5
mb90340 series 10 (continued) (top view) (fpt-100p-m05) * : mb90f342/f343/f345/f346/f347/f349/341/342/346/347/348/349 : x0a, x1a mb90f342s/f343s/f345s/f346s/f347s/f349s/341s/342s/346s/347s/348s/349s : p40,p41 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/int7 p76/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p32/wrl/wr/int10r p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47 p46 p45/frck1 p44/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 lqfp - 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 12345678910111213141516171819202122232425 p75/int5 p74/int4 p73/int3 p72/int2 p71/int1 p70/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 rst p31/rd/in5 p33/wrh p35/hak/out5
mb90340 series 11 ? mb90f342c (s) /mb90f343c (s) /mb90f345c (s) /mb90f346c (s) /mb90f347c (s) /mb90f349c (s) / mb90341c (s) /mb90342c (s) , mb90346c (s) /MB90347C (s) /mb90348c (s) /mb90349c (s) (continued) (top view) ( fpt - 100p - m06 ) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p75/an21/int5 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p56/an14 p55/an13 p54/an12/tot3 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 qfp - 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789101112131415161718192021222324252627282930 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p61/an1/ppg2(3) avss p57/an15 avcc p60/an0/ppg0(1) avrl avrh vss p62/an2/ppg4(5) p63/an3/ppg6(7) rst p31/rd/in5 p33/wrh p35/hak/out5 p32/wrl/wr/int10r * : mb90f342c/f343c/f345c/f346c/f347c/f349c/341c/342c/346c/347c/348c/349c : x0a, x1a mb90f342cs/f343cs/f345cs/f346cs/f347cs/f349cs/341cs/342cs/346cs/347cs/348cs/349cs : p40, p41
mb90340 series 12 (continued) (top view) (fpt-100p-m05) 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p04/ad04/int12 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 x1 vss vcc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/nt11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 x0 p00/ad00/int8 pa 1 / t x 0 pa0/rx0/int8r p97/out3 p96/out2 p95/out1 p94/out0 p93/ppg7(6) p92/ppg5(4) p91/ppg3(2) p90/ppg1(0) vss vcc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/sot0/tot2 p82/sin0/tin2/int14r p81/tot0/ckot/int13r p80/tin0/adtg/int12r p77/an23/int7 p76/an22/int6 md0 p26/a22/in2 p27/a23/in3 p30/ale/in4 p34/hrq/out4 p53/an11/tin3 p52/an10/sck2 p51/an9/sot2 p50/an8/sin2 p47/scl1 p46/sda1 p45/scl0/frck1 p44/sda0/frck0 p43/in7/tx1 p42/in6/rx1/int9r c vss vcc p41/x1a* p40/x0a* p37/clk/out7 p36/rdy/out6 99 p24/a20/in0 100 p25/a21/in1 28 p56/an14 27 p55/an13 26 p54/an12/tot3 49 md2 50 md1 78 p03/ad03/int11 77 p02/ad02/int10 76 p01/ad01/int9 lqfp - 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 12345678910111213141516171819202122232425 p75/an21/int5 p74/an20/int4 p73/an19/int3 p72/an18/int2 p71/an17/int1 p70/an16/int0 vss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg8(9) p63/an3/ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2(3) p60/an0/ppg0(1) avss avrl avrh avcc p57/an15 rst p31/rd/in5 p33/wrh p35/hak/out5 p32/wrl/wr/int10r * : mb90f342c/f343c/f345c/f346c/f347c/f349c/341c/342c/346c/347c/348c/349c : x0a, x1a mb90f342cs/f343cs/f345cs/f346cs/f347cs/f349cs/341cs/342cs/346cs/347cs/348cs/349cs : p40, p41
mb90340 series 13 n pin description (continued) pin no. pin name circuit type function lqfp100* 2 qfp100* 1 90 92 x1 a oscillation output 91 93 x0 oscillation input 52 54 rst e reset input 75 to 82 77 to 84 p00 to p07 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this function is enabled when the external bus is enabled. int8 to int15 external interrupt request input pins for int8 to int15. 83 85 p10 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad08 i/o pin for 8th bit of the external address/data bus. this function is enabled when the external bus is enabled. tin1 event input pin for the reload timer 1 84 86 p11 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad09 i/o pin for 9th bit of the external address/data bus. this function is enabled when the external bus is enabled. tot1 output pin for the reload timer 1 85 87 p12 n general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 i/o pin for 10th bit of the external address/data bus. this function is enabled when the external bus is enabled. sin3 serial data input pin for uart3 int11r sub external interrupt request input pin for int11 86 88 p13 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 i/o pin for 11th bit of the external address/data bus. this function is enabled when the external bus is enabled. sot3 serial data output pin for uart3 87 89 p14 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 i/o pin for 12th bit of the external address/data bus. this function is enabled when the external bus is enabled. sck3 clock i/o pin for uart3
mb90340 series 14 (continued) pin no. pin name circuit type function lqfp100 *2 qfp100 *1 92 94 p15 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 i/o pin for 13th bit of the external address/data bus. this function is enabled when the external bus is enabled. sin4 serial data input pin for uart4 (mb90v340 only) 93 95 p16 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 i/o pin for 14th bit of the external address/data bus. this function is enabled when the external bus is enabled. sot4 serial data output pin for uart4 (mb90v340 only) 94 96 p17 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 i/o pin for 15th bit of the external address/data bus. this func- tion is enabled when the external bus is enabled. sck4 clock i/o pin for uart4 (mb90v340 only) 95 to 98 97 to 100 p20 to p23 g general purpose i/o. the register can be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins for a16 to a19 of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pins are enabled as high address output pins (a16 to a19). ppg9,ppgb, ppgd,ppgf output pins for ppgs 99 to 2 1 to 4 p24 to p27 g general purpose i/o. the register can be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a20 to a23 output pins for a20 to a23 of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pins are enabled as high address output pins (a20 to a23). in0 to in3 data sample input pins for input captures icu0 to icu3 35 p30 g general purpose i/o.the register can be set to select whether to use a pull-up resistor.this function is enabled in single-chip mode. ale address latch enable output pin. this function is enabled when the external bus is enabled. in4 data sample input pin for input capture icu4
mb90340 series 15 (continued) pin no. pin name circuit type function lqfp100 *2 qfp100 *1 46 p31 g general purpose i/o.the register can be set to select whether to use a pull-up resistor.this function is enabled in single-chip mode. rd read strobe output pin for the data bus. this function is enabled when the external bus is enabled. in5 data sample input pin for input capture icu5 57 p32 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the wr /wrl pin output disabled. wrl / wr write strobe output pin for the data bus. this function is enabled when both the external bus and the wr /wrl pin output are en- abled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access while wr is used to write-strobe 8 bits of the data bus in 8-bit access. rx2 rx input pin for can2 interface (mb90v340 only) int10r sub external interrupt request input pin for int10 68 p33 g general purpose i/o. the register can be set to select whether to use a pull-up resistor.this function is enabled either in single-chip mode or with the wrh pin output disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled. tx2 tx output pin for can2 (mb90v340 only) 79 p34 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hrq hold request input pin. this function is enabled when both the ex- ternal bus and the hold function are enabled. out4 waveform output pin for output compare ocu4 810 p35 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compare ocu6 911 p36 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the external ready function disabled. rdy ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compare ocu5
mb90340 series 16 (continued) pin no. pin name circuit type function lqfp100 *2 qfp100 *1 10 12 p37 g general purpose i/o. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the clk output disabled. clk clk output pin. this function is enabled when both the external bus and clk output are enabled. out7 waveform output pin for output compare ocu7 11 to 12 13 to 14 p40 to p41 f general purpose i/o (devices with s-suffix) x0a , x1a b oscillator input pins for sub-clock (devices without s-suffix) 16 18 p42 f general purpose i/o in6 data sample input pin for input capture icu6 rx1 rx input pin for can1 interface (mb90f342/f343/f345/341/342 only) int9r sub external interrupt request input pin for int10 17 19 p43 f general purpose i/o in7 data sample input pin for input capture icu7 tx1 tx output pin for can1 (mb90f342/f343/f345/341/342 only) 18 20 p44 h general purpose i/o sda0 serial data i/o pin for i2c 0 (devices with c-suffix) frck0 input for the 16-bit i/o timer 0 19 21 p45 h general purpose i/o scl0 serial clock i/o pin for i2c 0 (devices with c-suffix) frck1 input for the 16-bit i/o timer 1 20 22 p46 h general purpose i/o sda1 serial data i/o pin for i2c 1 (devices with c-suffix) 21 23 p47 h general purpose i/o scl1 serial clock i/o pin for i 2 c 1 (devices with c-suffix) 22 24 p50 o general purpose i/o an8 analog input pin for the a/d converter sin2 serial data input pin for uart2 23 25 p51 i general purpose i/o an9 analog input pin for the a/d converter sot2 serial data output pin for uart2 24 26 p52 i general purpose i/o an10 analog input pin for the a/d converter sck2 clock i/o pin for uart2 25 27 p53 i general purpose i/o an11 analog input pin for the a/d converter tin3 event input pin for the reload timers 3
mb90340 series 17 (continued) pin no. pin name circuit type function lqfp100 *2 qfp100 *1 26 28 p54 i general purpose i/o an12 analog input pin for the a/d converter tot3 output pin for the reload timer 3 27 29 p55 i general purpose i/o an13 analog input pin for the a/d converter 28, 29 30, 31 p56 to p57 j general purpose i/o an14 to an15 analog input pin for the a/d converter da00 to da01 d/a converter analog output pins (mb90v340 only) 34 to 41 36 to 43 p60 to p67 i general purpose i/o an0 to an7 analog input pins for the a/d converter ppg0, 2, 4, 6, 8, a, c, e output pins for ppgs 43 to 48, 53, 54 45 to 50, 55, 56 p70 to p77 i general purpose i/o an16 to an23 analog input pins for the a/d converter (devices with c-suffix) int0 to int7 external interrupt request input pins for int0 to int7 55 57 p80 f general purpose i/o tin0 event input pin for the reload timers 0 adtg trigger input pin for the a/d converter int12r sub external interrupt request input pin for int12 56 58 p81 f general purpose i/o tot0 output pin for the reload timer 0 ckot output pin for the clock monitor int13r sub external interrupt request input pin for int13 57 59 p82 m general purpose i/o sin0 serial data input pin for uart0 tin2 event input pin for the reload timers 2 int14r sub external interrupt request input pin for int14 58 60 p83 f general purpose i/o sot0 serial data output pin for uart0 tot2 output pin for the reload timer 2 59 61 p84 f general purpose i/o sck0 clock i/o pin for uart0 int15r sub external interrupt request input pin for int15 60 62 p85 m general purpose i/o sin1 serial data input pin for uart1 61 63 p86 f general purpose i/o sot1 serial data output pin for uart1
mb90340 series 18 (continued) *1 : fpt-100p-m06 *2 : fpt-100p-m05 pin no. pin name circuit type function lqfp100 *2 qfp100 *1 62 64 p87 f general purpose i/o sck1 clock i/o pin for uart1 65 to 68 67 to 70 p90 to p93 f general purpose i/o ppg1, 3, 5, 7 output pins for ppgs 69 to 72 71 to 74 p94 to p97 f general purpose i/o out0 to out3 waveform output pins for output compares ocu0 to ocu3. this function is enabled when the ocu enables waveform output. 73 75 pa0 f general purpose i/o rx0 rx input pin for can0 interface int8r sub external interrupt request input pin for int8 74 76 pa1 f general purpose i/o tx0 tx output pin for can0 30 32 av cc k vcc power input pin for analog circuits 31 33 avrh l reference voltage input for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 32 34 avrl k lower reference voltage input for the a/d converter 33 35 av ss k vss power input pin for analog circuits 50, 51 52, 53 md1, md0 c input pins for specifying the operating mode. the pins must be directly connected to vcc or vss 49 51 md2 d input pin for specifying the operating mode. the pins must be directly connected to vcc or vss. 13 63 88 15 65 90 v cc ? power (3.5 v to 5.5 v) input pins 14 42 64 89 16 44 66 91 v ss ? power (0v) input pins 15 17 c k this is the power supply stabilization capacitor pin. it should be connected to a higher than or equal to 0.1 m f ceramic capaci- tor.
mb90340 series 19 n i/o circuit type (continued) type circuit remarks a oscillation circuit ? high-speed oscillation feedback resistor = approx. 1 m w b oscillation circuit ? low-speed oscillation feedback resistor = approx. 1 m w c mask rom and eva device: ? cmos hysteresis input pin ? resistor value : approx. 50 k w (typ) flash device: ? cmos input pin ? resistor value : approx. 50 k w (typ) d mask rom and eva device: ? cmos hysteresis input pin ? resistor value : approx. 50 k w (typ) ? pull-down resistor valule: approx. 50 k w flash device: ? cmos input pin ? resistor value : approx. 50 k w (typ) ? no pull-down e cmos hysteresis input pin ? resistor value : approx. 50 k w (typ) ? pull-up resistor valule: approx. 50 k w standby control signal x1 x0 xout standby control signal x1a x0a xout hysteresis inputs r pull-down resistor hysteresis inputs r pull-up resistor hysteresis inputs r
mb90340 series 20 (continued) type circuit remarks f ? cmos level output(i ol = 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) g ? cmos level output(i ol = 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the standby-time input shutdown function) ? programmalble pullup resistor: 50 k w approx. h ? cmos level output(i ol = 3 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) hysteresis inputs automotive inputs standby control for input shutdown pout nout r pull-up control hysteresis inputs automotive inputs ttl input standby control for input shutdown pout nout r hysteresis inputs automotive inputs standby control for input shutdown pout nout r
mb90340 series 21 (continued) type circuit remarks i ? cmos level output(i ol = 4 ma) ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input j ? cmos level output(i ol = 4 ma) ? d/a analg output ? cmos hysteresis inputs (with the stand- by-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input k ? power supply input protection circuit l ? a/d converter reference voltage power supply input pin, with the protection cir- cuit ? flash devices do not have a protection circuit against v cc for pin avrh hysteresis inputs automotive inputs standby control for input shutdown analog input pout nout r hysteresis inputs automotive inputs standby control for input shutdown analog input analog output pout nout r ane avr ane
mb90340 series 22 (continued) type circuit remarks m ? cmos level output(i ol = 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) n ? cmos level output(i ol = 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the standby-time input shutdown function) programmable pullup registor:50 k w approx o ? cmos level output(i ol = 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input cmos inputs automotive inputs standby control for input shutdown pout nout r pull-up control cmos inputs automotive inputs ttl input standby control for input shutdown pout nout r cmos inputs automotive inputs standby control for input shutdown analog input pout nout r
mb90340 series 23 n handling devices special care is required for the following when handling the device : ? preventing latch-up ? treatment of unused pins ? using external clock ? precautions for when not using a sub clock signal ? notes on during operation of pll clock mode ? power supply pins (v cc /v ss ) ? pull-up/down resistors ? crystal oscillator circuit ? turning-on sequence of power supply to a/d converter and analog inputs ? connection of unused pins of a/d converter ? notes on energization ? stabilization of power supply voltage ? initialization ? port0 to port3 output during power-on (external-bus mode) ? notes on using can function ? flash security function 1. preventing latch-up cmos ic chips may suffer latch - up under the following conditions : ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc and v ss . ?the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. handling unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k w . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 4. precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pin, and leave the x1a pin open. x0 x1 mb90340 series open
mb90340 series 24 5. notes on during operation of pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc /v ss ) ? if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. ? connect v cc and v ss to the device from the current supply source at a low impedance. ? as a measure against power supply noise, connect a capacitor of about 0.1 m f as a bypass capacitor between v cc and v ss in the vicinity of v cc and v ss pins of the device 7. pull-up/down resistors the mb90340 series does not support internal pull-up/down resistors (port 0 to port 3: built-in pull-up resistors). use external components where needed. 8. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. 9. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an14) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage not exceed avrh or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable) . 10. connection of unused pins of a/d converter if a/d converter is used connect unused pins of a/d converter to av cc = v cc , av ss = avrh = avrl = v ss . vcc vss vss vcc vss vcc mb90340 series vcc vss vcc vss
mb90340 series 25 11. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more m s (0.2 v to 2.7 v) 12. stabilization of power supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the specified v cc supply voltage operating range. therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz to 60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 13. initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, turn on the power again. 14. port 0 to port 3 output during power-on (external-bus mode) as shown below, when power is turned on in external-bus mode, there is a possibility that output signal of port 0 to port 3 might be unstable. 15. notes on using can function to use can function, please set 1 to direct bit of can direct mode register (cdmr). if direct bit is set to 0 (initial value), wait states will be performed when accessing can registers. please refer to hardware manual of mb90340 series for detail of can direct mode register. 16. flash security function (except for mb90f346) the security bit is located in the area of the flash memory. if protection code 01 h is written in the security bit, the flash memory is in the protected state by security. therefore please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security bit. flash memory size address for security bit mb90f347 embedded 1 mbit flash memory fe0001 h mb90f342 mb90f349 embedded 2 mbit flash memory fc0001 h mb90f343 embedded 3 mbit flash memory f90001 h mb90f345 embedded 4 mbit flash memory f80001 h v 5 dd dd v 3 port0 to port3 port0 to 3 outputs might be unstable port0 to 3 outputs = hi-z
mb90340 series 26 n block diagrams mb90v340(s) ram 30 k uart prescaler 10-bit adc 24 ch 16-bit reload timer 4 ch io timer 0 clock controller input capture 8 ch output compare 8 ch can controller external interrupt 16lx cpu fmc-16 bus x0,x1 rst sot4 to sot0 sck4 to sck0 sin4 to sin0 avcc avss an23 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 rx2 to rx0 tx2 to tx0 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a * 5 ch 10-bit dac 2 ch da01, da00 io timer 1 frck0 frck1 8/16-bit ppg 16 ch ppgf to ppg0 i 2 c interface sda1, sda0 scl1, scl0 3 ch 5 ch 2 ch dmac * : only for mb90v340 ( without s suffix ) clock monitor ckot (int15r to int8r) int7 to int0
mb90340 series 27 mb90f342/c (s) , mb90f343/c (s) , mb90f345/c (s) , mb90f346/c (s) , mb90f347/c (s) , mb90f349/c (s) , mb90341/c (s) , mb90342/c (s) , mb90346/c (s) , mb90347/c (s) , mb90348/c (s) , mb90349/c (s) ram rom/flash uart prescaler 10-bit adc 16/24 ch 16-bit reload timer 4 ch io timer 0 clock controller input capture 8 ch output compare 8 ch can controller external interrupt 16lx cpu fmc-16 bus x0,x1 rst sot3 to sot0 sck3 to sck0 sin3 to sin0 avcc avss an15 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 rx0, rx1* 3 tx0, tx1* 3 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wrl wrh hrq hak rdy clk x0a,x1a *1 64 k/128 k 4 ch io timer 1 frck0 frck1 8/16-bit ppg 16 ch ppgf to ppg0 1 ch/2 ch* 3 4 ch i 2 c interface sda1, sda0 *2 scl1, scl0 *2 2 ch an23 to an16 *2 2 k/6 k/16 k/ 20 k 256 k/384 k/ dmac *1 : only for devices without s suffix *2 : only for devices with c suffix *3 : supported by mb90341/c(s), 342/c(s), f342/c(s), f343/c(s), f345/c(s) only clock monitor ckot (int15r to int8r) int7 to int0 512 k
mb90340 series 28 n memory map mb90v340 ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h f8ffff h f80000 h 00ffff h 008000 h 007fff h 007900 h 0078ff h 000100 h 0000ef h 000000 h rom(ff bank) rom(fe bank) rom(fd bank) rom(fc bank) rom(fb bank) rom(fa bank) rom(f9 bank) rom(f8 bank) rom (image of ff bank) peripheral peripheral ram 30 k ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h f8ffff h f80000 h 00ffff h 008000 h 007fff h 007900 h 0050ff h 000100 h 0000ef h 000000 h peripheral ram 20 k peripheral rom (image of ff bank) rom(f8 bank) rom(f9 bank) rom(fa bank) rom(fb bank) rom(fc bank) rom(fd bank) rom(fe bank) rom(ff bank) mb90f345/c/s/cs mb90f343/c/s/cs rom(fd bank) rom(fe bank) rom(ff bank) ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h 00ffff h 008000 h 007fff h 007900 h 0050ff h 000100 h 0000ef h 000000 h rom(fb bank) rom(fa bank) rom(f9 bank) rom (image of ff bank) peripheral ram 20 k peripheral : no access
mb90340 series 29 note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, and its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 003fff h 000100 h 008000 h mb90349/c/s/cs mb90342/c/s/cs mb90f349/c/s/cs mb90f342/c/s/cs ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 003fff h 000100 h mb90348/c/s/cs mb90341/c/s/cs ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 000100 h 008000 h mb90347/c/s/cs mb90f347/c/s/cs 0018fe h ffffff h ff0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 000100 h 008000 h mb90346/c/s/cs mb90f346c/s/cs 0008ff h 007fff h 007900 h 008000 h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (image of ff bank) peripheral ram 16 k peripheral rom (ff bank) rom (fe bank) rom (image of ff bank) peripheral ram 16 k peripheral peripheral ram 6 k peripheral rom (image of ff bank) rom (fe bank) rom (ff bank) peripheral ram 2 k peripheral rom (image of ff bank) rom (ff bank) : no access
mb90340 series 30 n i/o map (continued) address register abbrevia- tion access resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx 0a h port a data register pdra r/w port a xxxxxxxx 0b h analog input enable port 5 ader5 r/w port 5, a/d 11111111 0c h analog input enable port 6 ader6 r/w port 6, a/d 11111111 0d h analog input enable port 7 ader7 r/w port 7, a/d 11111111 0e h input level select register 0 ilsr0 r/w ports xxxxxxxx 0f h input level select register 1 ilsr1 r/w ports xxxxxxxx 10 h port 0 direction register ddr0 r/w port 0 00000000 11 h port 1 direction register ddr1 r/w port 1 00000000 12 h port 2 direction register ddr2 r/w port 2 00000000 13 h port 3 direction register ddr3 r/w port 3 00000000 14 h port 4 direction register ddr4 r/w port 4 00000000 15 h port 5 direction register ddr5 r/w port 5 00000000 16 h port 6 direction register ddr6 r/w port 6 00000000 17 h port 7 direction register ddr7 r/w port 7 00000000 18 h port 8 direction register ddr8 r/w port 8 00000000 19 h port 9 direction register ddr9 r/w port 9 00000000 1a h port a direction register ddra r/w port a 00000100 1b h reserved 1c h port 0 pullup control register pucr0 r/w port 0 00000000 1d h port 1 pullup control register pucr1 r/w port 1 00000000 1e h port 2 pullup control register pucr2 r/w port 2 00000000 1f h port 3 pullup control register pucr3 w, r/w port 3 00000000
mb90340 series 31 (continued) address register abbrevia- tion access resource name initial value 20 h serial mode register smr0 w,r/w uart0 00000000 21 h serial control register scr0 w,r/w 00000000 22 h reception/transmission data register rdr0/ tdr0 r/w 00000000 23 h serial status register ssr0 r,r/w 00001000 24 h extended communication control reg. eccr0 r,w,r/ w 000000xx 25 h extended status/control register escr0 r/w 00000100 26 h baud rate register 0 bgr00 r/w 00000000 27 h baud rate register 1 bgr01 r/w 00000000 28 h serial mode register smr1 w,r/w uart1 00000000 29 h serial control register scr1 w,r/w 00000000 2a h reception/transmission data register rdr1/ tdr1 r/w 00000000 2b h serial status register ssr1 r,r/w 00001000 2c h extended communication control reg. eccr1 r,w, r/w 000000xx 2d h extended status/control register escr1 r/w 00000100 2e h baud rate register 0 bgr10 r/w 00000000 2f h baud rate register 1 bgr11 r/w 00000000 30 h ppg 0 operation mode control register ppgc0 w,r/w 16-bit programable pulse generator 0/1 0x000xx1 31 h ppg 1 operation mode control register ppgc1 w,r/w 0x000001 32 h ppg 0 and ppg 1 clock select register ppg01 r/w 000000x0 33 h reserved 34 h ppg 2 operation mode control register ppgc2 w,r/w 16-bit programable pulse generator 2/3 0x000xx1 35 h ppg 3 operation mode control register ppgc3 w,r/w 0x000001 36 h ppg 2 and ppg 3 clock select register ppg23 r/w 000000x0 37 h reserved 38 h ppg 4 operation mode control register ppgc4 w,r/w 16-bit programable pulse generator 4/5 0x000xx1 39 h ppg 5 operation mode control register ppgc5 w,r/w 0x000001 3a h ppg 4 and ppg 5 clock select register ppg45 r/w 000000x0 3b h rom correction control status 1 pacsr1 r/w rom correction 1 00000000 3c h ppg 6 operation mode control register ppgc6 w,r/w 16-bit programable pulse generator 6/7 0x000xx1 3d h ppg 7 operation mode control register ppgc7 w,r/w 0x000001 3e h ppg 6 and ppg 7 clock select register ppg67 r/w 000000x0 3f h reserved
mb90340 series 32 (continued) address register abbrevia- tion access resource name initial value 40 h ppg 8 operation mode control register ppgc8 w,r/w 16-bit programable pulse generator 8/9 0x000xx1 41 h ppg 9 operation mode control register ppgc9 w,r/w 0x000001 42 h ppg 8 and ppg 9 clock select register ppg89 r/w 000000x0 43 h reserved 44 h ppg a operation mode control register ppgca w,r/w 16-bit programable pulse generator a/b 0x000xx1 45 h ppg b operation mode control register ppgcb w,r/w 0x000001 46 h ppg a and ppg b clock select register ppgab r/w 000000x0 47 h reserved 48 h ppg c operation mode control register ppgcc w,r/w 16-bit programable pulse generator c/d 0x000xx1 49 h ppg d operation mode control register ppgcd w,r/w 0x000001 4a h ppg c and ppg d clock select register ppgcd r/w 000000x0 4b h reserved 4c h ppg e operation mode control register ppgce w,r/w 16-bit programable pulse generator e/f 0x000xx1 4d h ppg f operation mode control register ppgcf w,r/w 0x000001 4e h ppg e and ppg f clock select register ppgef r/w 000000x0 4f h reserved 50 h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 51 h input capture edge 0/1 ice01 r/w xxx0x0xx 52 h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 53 h input capture edge 2/3 ice23 r/w xxxxxxxx 54 h input capture control status 4/5 ics45 r/w input capture 4/5 00000000 55 h input capture edge 4/5 ice45 r/w xxxxxxxx 56 h input capture control status 6/7 ics67 r/w input capture 6/7 00000000 57 h input capture edge 6/7 ice67 r/w xxx000xx 58 h output compare control status 0 ocs0 r/w output compare 0/1 0000xx00 59 h output compare control status 1 ocs1 r/w 0xx00000 5a h output compare control status 2 ocs2 r/w output compare 2/3 0000xx00 5b h output compare control status 3 ocs3 r/w 0xx00000 5c h output compare control status 4 ocs4 r/w output compare 4/5 0000xx00 5d h output compare control status 5 ocs5 r/w 0xx00000 5e h output compare control status 6 ocs6 r/w output compare 6/7 0000xx00 5f h output compare control status 7 ocs7 r/w 0xx00000
mb90340 series 33 (continued) address register abbrevia- tion access resource name initial value 60 h timer control status 0 tmcsr0 r/w 16-bit reload timer 0 00000000 61 h timer control status 0 tmcsr0 r/w xxxx0000 62 h timer control status 1 tmcsr1 r/w 16-bit reload timer 1 00000000 63 h timer control status 1 tmcsr1 r/w xxxx0000 64 h timer control status 2 tmcsr2 r/w 16-bit reload timer 2 00000000 65 h timer control status 2 tmcsr2 r/w xxxx0000 66 h timer control status 3 tmcsr3 r/w 16-bit reload timer 3 00000000 67 h timer control status 3 tmcsr3 r/w xxxx0000 68 h a/d control status 0 adcs0 r/w a/d converter 000xxxx0 69 h a/d control status 1 adcs1 r/w 0000000x 6a h a/d data 0 adcr0 r 00000000 6b h a/d data 1 adcr1 r xxxxxx00 6c h adc setting 0 adsr0 r/w 00000000 6d h adc setting 1 adsr1 r/w 00000000 6e h reserved 6f h rom mirror romm w rom mirror xxxxxxx1 70 h to 8f h reserved for can interface 0/1. refer to n can controllers 90 h to 9a h reserved 9b h dma descriptor channel select dcsr r/w dma 00000000 9c h dma status l dsrl r/w 00000000 9d h dma status h dsrh r/w 00000000 9e h rom correction control status 0 pacsr0 r/w rom correction 0 00000000 9f h delayed interrupt/release dirr r/w delayed interrupt xxxxxxx0 a0 h low-power mode control lpmcr w,r/w low power controller 00011000 a1 h clock selection ckscr r,r/w low power controller 11111100 a2 h , a3 h reserved a4 h dma stop status dssr r/w dma 00000000 a5 h automatic ready function select reg. arsr w external memory access 0011xx00 a6 h external address output control reg. hacr w 00000000 a7 h bus control signal selection register ecsr w 0000000x a8 h watchdog control wdtc r,w watchdog timer xxxxx111 a9 h time base timer control tbtc w,r/w time base timer 1xx00100
mb90340 series 34 (continued) address register abbrevia- tion access resource name initial value aa h watch timer control register wtc r,r/w watch timer 1x001000 ab h reserved ac h dma enable l derl r/w dma 00000000 ad h dma enable h derh r/w 00000000 ae h flash control status (flashdevices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 af h reserved b0 h interrupt control register 00 icr00 w,r/w interrupt controller 00000111 b1 h interrupt control register 01 icr01 w,r/w 00000111 b2 h interrupt control register 02 icr02 w,r/w 00000111 b3 h interrupt control register 03 icr03 w,r/w 00000111 b4 h interrupt control register 04 icr04 w,r/w 00000111 b5 h interrupt control register 05 icr05 w,r/w 00000111 b6 h interrupt control register 06 icr06 w,r/w 00000111 b7 h interrupt control register 07 icr07 w,r/w 00000111 b8 h interrupt control register 08 icr08 w,r/w 00000111 b9 h interrupt control register 09 icr09 w,r/w 00000111 ba h interrupt control register 10 icr10 w,r/w 00000111 bb h interrupt control register 11 icr11 w,r/w 00000111 bc h interrupt control register 12 icr12 w,r/w 00000111 bd h interrupt control register 13 icr13 w,r/w 00000111 be h interrupt control register 14 icr14 w,r/w 00000111 bf h interrupt control register 15 icr15 w,r/w 00000111 c0 h d/a converter data 0 dat0 r/w d/a converter xxxxxxxx c1 h d/a converter data 1 dat1 r/w xxxxxxxx c2 h d/a control 0 dacr0 r/w xxxxxxx0 c3 h d/a control 1 dacr1 r/w xxxxxxx0 c4 h , c5 h reserved c6 h external interrupt enable 0 enir0 r/w external interrupt 0 00000000 c7 h external interrupt request 0 eirr0 r/w xxxxxxxx c8 h external interrupt level 0 elvr0 r/w 00000000 c9 h external interrupt level 0 elvr0 r/w 00000000
mb90340 series 35 (continued) address register abbrevia- tion access resource name initial value ca h external interrupt enable 1 enir1 r/w external interrupt 1 00000000 cb h external interrupt request 1 eirr1 r/w xxxxxxxx cc h external interrupt level 1 elvr1 r/w 00000000 cd h external interrupt level 1 elvr1 r/w 00000000 ce h external interrupt 1 source select eissr r/w 00000000 cf h pll/subclock control register psccr w pll xxxx0000 d0 h dma buffer addrss pointer l bapl r/w dma xxxxxxxx d1 h dma buffer addrss pointer m bapm r/w xxxxxxxx d2 h dma buffer addrss pointer h baph r/w xxxxxxxx d3 h dma control dmacs r/w xxxxxxxx d4 h i/o register address pointer l ioal r/w xxxxxxxx d5 h i/o register address pointer h ioah r/w xxxxxxxx d6 h data counter l dctl r/w xxxxxxxx d7 h data counter h dcth r/w xxxxxxxx d8 h serial mode register smr2 w,r/w uart2 00000000 d9 h serial control register scr2 w,r/w 00000000 da h reception/transmission data register rdr2/ tdr2 r/w 00000000 db h serial status register ssr2 r,r/w 00001000 dc h extended communication control reg. eccr2 r,w, r/w 000000xx dd h extended status/control register escr2 r/w 00000100 de h baud rate register 0 bgr20 r/w 00000000 df h baud rate register 1 bgr21 r/w 00000000 e0 h to ef h reserved for can interface 2. refer to n can controllers f0 h to ff h external
mb90340 series 36 (continued) address register abbrevia- tion access resource name initial value 7900 h reload l prll0 r/w 16-bit programable pulse generator 0/1 xxxxxxxx 7901 h reload h prlh0 r/w xxxxxxxx 7902 h reload l prll1 r/w xxxxxxxx 7903 h reload h prlh1 r/w xxxxxxxx 7904 h reload l prll2 r/w 16-bit programable pulse generator 2/3 xxxxxxxx 7905 h reload h prlh2 r/w xxxxxxxx 7906 h reload l prll3 r/w xxxxxxxx 7907 h reload h prlh3 r/w xxxxxxxx 7908 h reload l prll4 r/w 16-bit programable pulse generator 4/5 xxxxxxxx 7909 h reload h prlh4 r/w xxxxxxxx 790a h reload l prll5 r/w xxxxxxxx 790b h reload h prlh5 r/w xxxxxxxx 790c h reload l prll6 r/w 16-bit programable pulse generator 6/7 xxxxxxxx 790d h reload h prlh6 r/w xxxxxxxx 790e h reload l prll7 r/w xxxxxxxx 790f h reload h prlh7 r/w xxxxxxxx 7910 h reload l prll8 r/w 16-bit programable pulse generator 8/9 xxxxxxxx 7911 h reload h prlh8 r/w xxxxxxxx 7912 h reload l prll9 r/w xxxxxxxx 7913 h reload h prlh9 r/w xxxxxxxx 7914 h reload l prlla r/w 16-bit programable pulse generator a/b xxxxxxxx 7915 h reload h prlha r/w xxxxxxxx 7916 h reload l prllb r/w xxxxxxxx 7917 h reload h prlhb r/w xxxxxxxx 7918 h reload l prllc r/w 16-bit programable pulse generator c/d xxxxxxxx 7919 h reload h prlhc r/w xxxxxxxx 791a h reload l prlld r/w xxxxxxxx 791b h reload h prlhd r/w xxxxxxxx 791c h reload l prlle r/w 16-bit programable pulse generator e/f xxxxxxxx 791d h reload h prlhe r/w xxxxxxxx 791e h reload l prllf r/w xxxxxxxx 791f h reload h prlhf r/w xxxxxxxx 7920 h input capture 0 ipcp0 r input capture 0/1 xxxxxxxx 7921 h input capture 0 ipcp0 r xxxxxxxx 7922 h input capture 1 ipcp1 r xxxxxxxx 7923 h input capture 1 ipcp1 r xxxxxxxx
mb90340 series 37 (continued) address register abbrevia- tion access resource name initial value 7924 h input capture 2 ipcp2 r input capture 2/3 xxxxxxxx 7925 h input capture 2 ipcp2 r xxxxxxxx 7926 h input capture 3 ipcp3 r xxxxxxxx 7927 h input capture 3 ipcp3 r xxxxxxxx 7928 h input capture 4 ipcp4 r input capture 4/5 xxxxxxxx 7929 h input capture 4 ipcp4 r xxxxxxxx 792a h input capture 5 ipcp5 r xxxxxxxx 792b h input capture 5 ipcp5 r xxxxxxxx 792c h input capture 6 ipcp6 r input capture 6/7 xxxxxxxx 792d h input capture 6 ipcp6 r xxxxxxxx 792e h input capture 7 ipcp7 r xxxxxxxx 792f h input capture 7 ipcp7 r xxxxxxxx 7930 h output compare 0 occp0 r/w output compare 0/1 xxxxxxxx 7931 h output compare 0 occp0 r/w xxxxxxxx 7932 h output compare 1 occp1 r/w xxxxxxxx 7933 h output compare 1 occp1 r/w xxxxxxxx 7934 h output compare 2 occp2 r/w output compare 2/3 xxxxxxxx 7935 h output compare 2 occp2 r/w xxxxxxxx 7936 h output compare 3 occp3 r/w xxxxxxxx 7937 h output compare 3 occp3 r/w xxxxxxxx 7938 h output compare 4 occp4 r/w output compare 4/5 xxxxxxxx 7939 h output compare 4 occp4 r/w xxxxxxxx 793a h output compare 5 occp5 r/w xxxxxxxx 793b h output compare 5 occp5 r/w xxxxxxxx 793c h output compare 6 occp6 r/w output compare 6/7 xxxxxxxx 793d h output compare 6 occp6 r/w xxxxxxxx 793e h output compare 7 occp7 r/w xxxxxxxx 793f h output compare 7 occp7 r/w xxxxxxxx 7940 h timer data 0 tcdt0 r/w i/o timer 0 00000000 7941 h timer data 0 tcdt0 r/w 00000000 7942 h timer control 0 tccsl0 r/w 00000000 7943 h timer control 0 tccsh0 r/w 0xxxxxxx 7944 h timer data 1 tcdt1 r/w i/o timer 1 00000000 7945 h timer data 1 tcdt1 r/w 00000000 7946 h timer control 1 tccsl1 r/w 00000000 7947 h timer control 1 tccsh1 r/w 0xxxxxxx
mb90340 series 38 (continued) address register abbrevia- tion access resource name initial value 7948 h timer 0/reload 0 tmr0/ tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx 7949 h r/w xxxxxxxx 794a h timer 1/reload 1 tmr1/ tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx 794b h r/w xxxxxxxx 794c h timer 2/reload 2 tmr2/ tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx 794d h r/w xxxxxxxx 794e h timer 3/reload 3 tmr3/ tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx 794f h r/w xxxxxxxx 7950 h serial mode register smr3 w,r/w uart3 00000000 7951 h serial control register scr3 w,r/w 00000000 7952 h reception/transmission data register rdr3/ tdr3 r/w 00000000 7953 h serial status register ssr3 r,r/w 00001000 7954 h extended communication control reg. eccr3 r,w, r/w 000000xx 7955 h extended status/control register escr3 r/w 00000100 7956 h baud rate register 0 bgr30 r/w 00000000 7957 h baud rate register 1 bgr31 r/w 00000000 7958 h serial mode register smr4 w,r/w uart4 00000000 7959 h serial control register scr4 w,r/w 00000000 795a h reception/transmission data register rdr4/ tdr4 r/w 00000000 795b h serial status register ssr4 r,r/w 00001000 795c h extended communication control reg. eccr4 r,w, r/w 000000xx 795d h extended status/control register escr4 r/w 00000100 795e h baud rate register 0 bgr40 r/w 00000000 795f h baud rate register 1 bgr41 r/w 00000000 7960 h to 796b h reserved 796c h clock output enable register clkr r/w clock monitor xxxx0000 796d h reserved 796e h can direct mode register cdmr r/w can clock sync xxxxxxx0 796f h can rx/tx redirect register canswr r/w can 0/1 xxxxxx00
mb90340 series 39 (continued) address register abbrevia- tion access resource name initial value 7970 h i 2 c bus status register ibsr0 r i 2 c interface 0 00000000 7971 h i 2 c bus control register ibcr0 w,r/w 00000000 7972 h i 2 c 10 bit slave address register itbal0 r/w 00000000 7973 h itbah0 r/w 00000000 7974 h i 2 c 10 bit address mask register itmkl0 r/w 11111111 7975 h itmkh0 r/w 00111111 7976 h i 2 c 7 bit slave address register isba0 r/w 00000000 7977 h i 2 c 7 bit address mask register ismk0 r/w 01111111 7978 h i 2 c data register idar0 r/w 00000000 7979 h , 797a h reserved 797b h i 2 c clock control register iccr0 r/w i 2 c interface 0 00011111 797c h to 797f h reserved 7980 h i 2 c bus status register ibsr1 r i 2 c interface 1 00000000 7981 h i 2 c bus control register ibcr1 w,r/w 00000000 7982 h i 2 c 10 bit slave address register itbal1 r/w 00000000 7983 h itbah1 r/w 00000000 7984 h i 2 c 10 bit address mask register itmkl1 r/w 11111111 7985 h itmkh1 r/w 00111111 7986 h i 2 c 7 bit slave address register isba1 r/w 00000000 7987 h i 2 c 7 bit address mask register ismk1 r/w 01111111 7988 h i 2 c data register idar1 r/w 00000000 7989 h , 798a h reserved 798b h i 2 c clock control register iccr1 r/w i 2 c interface 1 00011111 798c h to 79c1 h reserved 79c2 h clock modulator control register cmcr r,r/w clock modulator 0001x000 79c3 h to 79df h reserved
mb90340 series 40 (continued) notes : initial value of x represents unknown value. addresses in the range 0000 h to 00bf h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results reading x and any write access should not be performed. address register abbrevia- tion access resource name initial value 79e0 h rom correction address 0 padr0 r/w rom correction 0 xxxxxxxx 79e1 h rom correction address 0 padr0 r/w xxxxxxxx 79e2 h rom correction address 0 padr0 r/w xxxxxxxx 79e3 h rom correction address 1 padr1 r/w xxxxxxxx 79e4 h rom correction address 1 padr1 r/w xxxxxxxx 79e5 h rom correction address 1 padr1 r/w xxxxxxxx 79e6 h rom correction address 2 padr2 r/w xxxxxxxx 79e7 h rom correction address 2 padr2 r/w xxxxxxxx 79e8 h rom correction address 2 padr2 r/w xxxxxxxx 79e9 h to 79ef h reserved 79f0 h rom correction address 3 padr3 r/w rom correction 1 xxxxxxxx 79f1 h rom correction address 3 padr3 r/w xxxxxxxx 79f2 h rom correction address 3 padr3 r/w xxxxxxxx 79f3 h rom correction address 4 padr4 r/w xxxxxxxx 79f4 h rom correction address 4 padr4 r/w xxxxxxxx 79f5 h rom correction address 4 padr4 r/w xxxxxxxx 79f6 h rom correction address 5 padr5 r/w xxxxxxxx 79f7 h rom correction address 5 padr5 r/w xxxxxxxx 79f8 h rom correction address 5 padr5 r/w xxxxxxxx 79f9 h to 79ff h reserved 7a00 h to 7aff h reserved for can interface 0. refer to n can controllers 7b00 h to 7bff h reserved for can interface 0. refer to n can controllers 7c00 h to 7cff h reserved for can interface 1. refer to n can controllers 7d00 h to 7dff h reserved for can interface 1. refer to n can controllers 7e00 h to 7eff h reserved for can interface 2. refer to n can controllers 7f00 h to 7fff h reserved for can interface 2. refer to n can controllers
mb90340 series 41 n can controllers the can controller has the following features : ? conforms to can specification version 2.0 part a and b supports transmission/reception in standard frame and extended frame formats ? supports transmitting of data frames by receiving remote frames ? 16 transmitting/receiving message buffers 29-bit id and 8-byte data multi-level message buffer configuration ? provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as id acceptance mask two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbits/s to 2 mbits/s (when input clock is at 16 mhz) list of control registers (1) address register abbreviation access initial value can0 can1 can2 000070 h 000080 h 0000e0 h message buffer valid register bvalr r/w 00000000 00000000 000071 h 000081 h 0000e1 h 000072 h 000082 h 0000e2 h transmit request register treqr r/w 00000000 00000000 000073 h 000083 h 0000e3 h 000074 h 000084 h 0000e4 h transmit cancel register tcanr w 00000000 00000000 000075 h 000085 h 0000e5 h 000076 h 000086 h 0000e6 h transmission complete register tcr r/w 00000000 00000000 000077 h 000087 h 0000e7 h 000078 h 000088 h 0000e8 h receive complete register rcr r/w 00000000 00000000 000079 h 000089 h 0000e9 h 00007a h 00008a h 0000ea h remote request receiving register rrtrr r/w 00000000 00000000 00007b h 00008b h 0000eb h 00007c h 00008c h 0000ec h receive overrun register rovrr r/w 00000000 00000000 00007d h 00008d h 0000ed h 00007e h 00008e h 0000ee h reception interrupt enable register rier r/w 00000000 00000000 00007f h 00008f h 0000ef h
mb90340 series 42 list of control registers (2) address register abbreviation access initial value can0 can1 can2 007b00 h 007d00 h 007f00 h control status register csr r/w, w r/w, r 0xxxx0x1 00xxx000 007b01 h 007d01 h 007f01 h 007b02 h 007d02 h 007f02 h last event indicator register leir r/w 000x0000 xxxxxxxx 007b03 h 007d03 h 007f03 h 007b04 h 007d04 h 007f04 h receive/transmit error counter rtec r 00000000 00000000 007b05 h 007d05 h 007f05 h 007b06 h 007d06 h 007f06 h bit timing register btr r/w 11111111 x1111111 007b07 h 007d07 h 007f07 h 007b08 h 007d08 h 007f08 h ide register ider r/w xxxxxxxx xxxxxxxx 007b09 h 007d09 h 007f09 h 007b0a h 007d0a h 007f0a h transmit rtr register trtrr r/w 00000000 00000000 007b0b h 007d0b h 007f0b h 007b0c h 007d0c h 007f0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx 007b0d h 007d0d h 007f0d h 007b0e h 007d0e h 007f0e h transmit interrupt enable register tier r/w 00000000 00000000 007b0f h 007d0f h 007f0f h 007b10 h 007d10 h 007f10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx 007b11 h 007d11 h 007f11 h 007b12 h 007d12 h 007f12 h xxxxxxxx xxxxxxxx 007b13 h 007d13 h 007f13 h 007b14 h 007d14 h 007f14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx 007b15 h 007d15 h 007f15 h 007b16 h 007d16 h 007f16 h xxxxxxxx xxxxxxxx 007b17 h 007d17 h 007f17 h 007b18 h 007d18 h 007f18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx 007b19 h 007d19 h 007f19 h 007b1a h 007d1a h 007f1a h xxxxxxxx xxxxxxxx 007b1b h 007d1b h 007f1b h
mb90340 series 43 list of message buffers (id registers) (1) address register abbreviation access initial value can0 can1 can2 007a00 h to 007a1f h 007c00 h to 007c1f h 007e00 h to 007e1f h general- purpose ram ? r/w xxxxxxxx to xxxxxxxx 007a20 h 007c20 h 007e20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx 007a21 h 007c21 h 007e21 h 007a22 h 007c22 h 007e22 h xxxxxxxx xxxxxxxx 007a23 h 007c23 h 007e23 h 007a24 h 007c24 h 007e24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx 007a25 h 007c25 h 007e25 h 007a26 h 007c26 h 007e26 h xxxxxxxx xxxxxxxx 007a27 h 007c27 h 007e27 h 007a28 h 007c28 h 007e28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx 007a29 h 007c29 h 007e29 h 007a2a h 007c2a h 007e2a h xxxxxxxx xxxxxxxx 007a2b h 007c2b h 007e2b h 007a2c h 007c2c h 007e2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx 007a2d h 007c2d h 007e2d h 007a2e h 007c2e h 007e2e h xxxxxxxx xxxxxxxx 007a2f h 007c2f h 007e2f h 007a30 h 007c30 h 007e30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx 007a31 h 007c31 h 007e31 h 007a32 h 007c32 h 007e32 h xxxxxxxx xxxxxxxx 007a33 h 007c33 h 007e33 h 007a34 h 007c34 h 007e34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx 007a35 h 007c35 h 007e35 h 007a36 h 007c36 h 007e36 h xxxxxxxx xxxxxxxx 007a37 h 007c37 h 007e37 h 007a38 h 007c38 h 007e38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx 007a39 h 007c39 h 007e39 h 007a3a h 007c3a h 007e3a h xxxxxxxx xxxxxxxx 007a3b h 007c3b h 007e3b h 007a3c h 007c3c h 007e3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx 007a3d h 007c3d h 007e3d h 007a3e h 007c3e h 007e3e h xxxxxxxx xxxxxxxx 007a3f h 007c3f h 007e3f h
mb90340 series 44 list of message buffers (id registers) (2) address register abbreviation access initial value can0 can1 can2 007a40 h 007c40 h 007e40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx 007a41 h 007c41 h 007e41 h 007a42 h 007c42 h 007e42 h xxxxxxxx xxxxxxxx 007a43 h 007c43 h 007e43 h 007a44 h 007c44 h 007e44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx 007a45 h 007c45 h 007e45 h 007a46 h 007c46 h 007e46 h xxxxxxxx xxxxxxxx 007a47 h 007c47 h 007e47 h 007a48 h 007c48 h 007e48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx 007a49 h 007c49 h 007e49 h 007a4a h 007c4a h 007e4a h xxxxxxxx xxxxxxxx 007a4b h 007c4b h 007e4b h 007a4c h 007c4c h 007e4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx 007a4d h 007c4d h 007e4d h 007a4e h 007c4e h 007e4e h xxxxxxxx xxxxxxxx 007a4f h 007c4f h 007e4f h 007a50 h 007c50 h 007e50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx 007a51 h 007c51 h 007e51 h 007a52 h 007c52 h 007e52 h xxxxxxxx xxxxxxxx 007a53 h 007c53 h 007e53 h 007a54 h 007c54 h 007e54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx 007a55 h 007c55 h 007e55 h 007a56 h 007c56 h 007e56 h xxxxxxxx xxxxxxxx 007a57 h 007c57 h 007e57 h 007a58 h 007c58 h 007e58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx 007a59 h 007c59 h 007e59 h 007a5a h 007c5a h 007e5a h xxxxxxxx xxxxxxxx 007a5b h 007c5b h 007e5b h 007a5c h 007c5c h 007e5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx 007a5d h 007c5d h 007e5d h 007a5e h 007c5e h 007e5e h xxxxxxxx xxxxxxxx 007a5f h 007c5f h 007e5f h
mb90340 series 45 list of message buffers (dlc registers and data registers) (1) address register abbreviation access initial value can0 can1 can2 007a60 h 007c60 h 007e60 h dlc register 0 dlcr0 r/w xxxxxxxx 007a61 h 007c61 h 007e61 h 007a62 h 007c62 h 007e62 h dlc register 1 dlcr1 r/w xxxxxxxx 007a63 h 007c63 h 007e63 h 007a64 h 007c64 h 007e64 h dlc register 2 dlcr2 r/w xxxxxxxx 007a65 h 007c65 h 007e65 h 007a66 h 007c66 h 007e66 h dlc register 3 dlcr3 r/w xxxxxxxx 007a67 h 007c67 h 007e67 h 007a68 h 007c68 h 007e68 h dlc register 4 dlcr4 r/w xxxxxxxx 007a69 h 007c69 h 007e69 h 007a6a h 007c6a h 007e6a h dlc register 5 dlcr5 r/w xxxxxxxx 007a6b h 007c6b h 007e6b h 007a6c h 007c6c h 007e6c h dlc register 6 dlcr6 r/w xxxxxxxx 007a6d h 007c6d h 007e6d h 007a6e h 007c6e h 007e6e h dlc register 7 dlcr7 r/w xxxxxxxx 007a6f h 007c6f h 007e6f h 007a70 h 007c70 h 007e70 h dlc register 8 dlcr8 r/w xxxxxxxx 007a71 h 007c71 h 007e71 h 007a72 h 007c72 h 007e72 h dlc register 9 dlcr9 r/w xxxxxxxx 007a73 h 007c73 h 007e73 h 007a74 h 007c74 h 007e74 h dlc register 10 dlcr10 r/w xxxxxxxx 007a75 h 007c75 h 007e75 h 007a76 h 007c76 h 007e76 h dlc register 11 dlcr11 r/w xxxxxxxx 007a77 h 007c77 h 007e77 h 007a78 h 007c78 h 007e78 h dlc register 12 dlcr12 r/w xxxxxxxx 007a79 h 007c79 h 007e79 h 007a7a h 007c7a h 007e7a h dlc register 13 dlcr13 r/w xxxxxxxx 007a7b h 007c7b h 007e7b h 007a7c h 007c7c h 007e7c h dlc register 14 dlcr14 r/w xxxxxxxx 007a7d h 007c7d h 007e7d h 007a7e h 007c7e h 007e7e h dlc register 15 dlcr15 r/w xxxxxxxx 007a7f h 007c7f h 007e7f h
mb90340 series 46 list of message buffers (dlc registers and data registers) (2) address register abbreviation access initial value can0 can1 can2 007a80 h to 007a87 h 007c80 h to 007c87 h 007e80 h to 007e87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx to xxxxxxxx 007a88 h to 007a8f h 007c88 h to 007c8f h 007e88 h to 007e8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx to xxxxxxxx 007a90 h to 007a97 h 007c90 h to 007c97 h 007e90 h to 007e97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx to xxxxxxxx 007a98 h to 007a9f h 007c98 h to 007c9f h 007e98 h to 007e9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx to xxxxxxxx 007aa0 h to 007aa7 h 007ca0 h to 007ca7 h 007ea0 h to 007ea7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx to xxxxxxxx 007aa8 h to 007aaf h 007ca8 h to 007caf h 007ea8 h to 007eaf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx to xxxxxxxx 007ab0 h to 007ab7 h 007cb0 h to 007cb7 h 007eb0 h to 007eb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx to xxxxxxxx 007ab8 h to 007abf h 007cb8 h to 007cbf h 007eb8 h to 007ebf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx to xxxxxxxx 007ac0 h to 007ac7 h 007cc0 h to 007cc7 h 007ec0 h to 007ec7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx to xxxxxxxx 007ac8 h to 007acf h 007cc8 h to 007ccf h 007ec8 h to 007ecf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx to xxxxxxxx 007ad0 h to 007ad7 h 007cd0 h to 007cd7 h 007ed0 h to 007ed7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx to xxxxxxxx 007ad8 h to 007adf h 007cd8 h to 007cdf h 007ed8 h to 007edf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx to xxxxxxxx 007ae0 h to 007ae7 h 007ce0 h to 007ce7 h 007ee0 h to 007ee7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx to xxxxxxxx 007ae8 h to 007aef h 007ce8 h to 007cef h 007ee8 h to 007eef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx to xxxxxxxx
mb90340 series 47 list of message buffers (dlc registers and data registers) (3) address register abbreviation access initial value can0 can1 can2 007af0 h to 007af7 h 007cf0 h to 007cf7 h 007ef0 h to 007ef7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx to xxxxxxxx 007af8 h to 007aff h 007cf8 h to 007cff h 007ef8 h to 007eff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx to xxxxxxxx
mb90340 series 48 n interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? can 0 rx n ? #11 ffffd0 h icr00 0000b0 h can 0 tx/ns n ? #12 ffffcc h can 1 rx / input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h can 1 tx/ns / input capture 7 y1 ? #14 ffffc4 h can 2 rx / i 2 c0 n ? #15 ffffc0 h icr02 0000b2 h can 2 tx/ns n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 0/1/4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 2/3/6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h time base timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 0 to 3, 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 4 to 7, 12 to 15 y1 4 #28 ffff8c h a/d converter y1 5 #29 ffff88 h icr09 0000b9 h i/o timer 0 / i/o timer 1 n ? #30 ffff84 h input capture 4/5 / i 2 c1 y1 6 #31 ffff80 h icr10 0000ba h output compare 0/1/4/5 y1 7 #32 ffff7c h input capture 0 to 3 y1 8 #33 ffff78 h icr11 0000bb h output compare 2/3/6/7 y1 9 #34 ffff74 h uart 0 rx y2 10 #35 ffff70 h icr12 0000bc h uart 0 tx y1 11 #36 ffff6c h uart 1 rx / uart 3 rx y2 12 #37 ffff68 h icr13 0000bd h uart 1 tx / uart 3 tx y1 13 #38 ffff64 h
mb90340 series 49 (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : the peripheral resources sharing the icr register have the same interrupt level. when two peripheral resources share the icr register, only one can use extended intelligent i/o service at a time. when either of the two peripheral resources sharing the icr register specifies extended intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address uart 2 rx / uart 4 rx y2 14 #39 ffff60 h icr14 0000be h uart 2 tx / uart 4 tx y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h
mb90340 series 50 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 avrh, avrl v ss - 0.3 v ss + 6.0 v av cc 3 avrh, av cc 3 avrl, avrh 3 avrl input voltage v i v ss - 0.3 v ss + 6.0 v *2 output voltage v o v ss - 0.3 v ss + 6.0 v *2 maximum clamp current i clamp - 4.0 + 4.0 ma *4 total maximum clamp current s |i clamp | ? 40 ma *4 l level maximum output current i ol ? 15 ma *3 l level average output current i olav ? 4ma*3 l level maximum overall output current s i ol ? 100 ma *3 l level average overall output current s i olav ? 50 ma *3 h level maximum output current i oh ?- 15 ma *3 h level average output current i ohav ?- 4ma*3 h level maximum overall output current s i oh ?- 100 ma *3 h level average overall output current s i ohav ?- 50 ma *3 power consumption p d ? 340 mw mb90f347 operating temperature t a - 40 + 105 c storage temperature t stg - 55 + 150 c
mb90340 series 51 (continued) *1: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *2: v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximun current to/from an input is limited by some means with external components, the i clamp rating supercedes the v i rating. *3: applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa1 *4: applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67 p70 to p77, p80 to p87, p90 to p97, pa0 to pa1 use within recommended operating conditions. use at dc voltage (current) the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. sample recommended circuits: warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90340 series 52 2. recommended conditions (v ss = av ss = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smooth capacitor c s 0.1 ? 1.0 m f use a ceramic capacitor or capac- itor of better ac characteristics. capacitor at the v cc should be greater than this capacitor. operating temperature t a - 40 ?+ 105 c c c s c pin connection diagram
mb90340 series 53 3. dc characteristics (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max input h voltage (at v cc = 5 v 10 % ) v ihs ?? 0.8 v cc ? v cc + 0.3 v port inputs if cmos hysteresis input levels are selected (except uart sin input pins and i 2 c input pins) v iha ?? 0.8 v cc ? v cc + 0.3 v port inputs if automotive input levels are selected v iht ?? 2.0 ? v cc + 0.3 v port inputs if ttl input levels are selected v ihs ?? 0.7 v cc ? v cc + 0.3 v uart sin inputs if cmos input levels are selected v ihi ?? 0.7 v cc ? v cc + 0.3 v i 2 c port inputs if cmos hysteresis input levels are selected v ihr ?? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc - 0.3 ? v cc + 0.3 v md input pin input l voltage (at v cc = 5 v 10 % ) v ils ?? v ss - 0.3 ? 0.2 v cc v port inputs if cmos hysteresis input levels are selected (except uart sin input pins and i 2 c input pins) v ila ?? v ss - 0.3 ? 0.5 v cc v port inputs if automotive input levels are selected v ilt ?? v ss - 0.3 ? 0.8 v port inputs if ttl input levels are selected v ils ?? v ss - 0.3 ? 0.3 v cc v uart sin inputs if cmos input levels are selected v ili ?? v ss - 0.3 ? 0.3 v cc v i 2 c port inputs if cmos hysteresis input levels are selected v ilr ?? v ss - 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss - 0.3 ? v ss + 0.3 v md input pin output h voltage v oh normal outputs v cc = 4.5 v, i oh = - 4.0 ma v cc - 0.5 ?? v output h voltage v ohi i 2 c current outputs v cc = 4.5 v, i oh = - 3.0 ma v cc - 0.5 ?? v output l voltage v ol normal outputs v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v output l voltage v oli i 2 c current outputs v cc = 4.5 v, i ol = 3.0 ma ?? 0.4 v
mb90340 series 54 (continued) (t a = - 40 c to + 105, v cc = 5.0 v 10 % , v ss = av ss = 0 v) * : current values are tentative. they are subject to change without notice according to improvements in the characteristics. the power supply current is measured with an external clock. parameter sym- bol pin condition value unit remarks min typ max input leak current i il ? v cc = 5.5 v, v ss < v i < v cc - 1 ? 1 m a pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k w pull-down resistance r down md2 ? 25 50 100 k w except flash devices power supply current* i cc v cc v cc = 5.0 v, internal frequency : 24 mhz, at normal operation. ? 55 70 ma mb90f347 v cc = 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 70 85 ma mb90f347 v cc = 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 75 90 ma mb90f347 i ccs v cc = 5.0 v, internal frequency : 24 mhz, at sleep mode. ? 25 35 ma mb90f347 i cts v cc = 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.8 ma mb90f347 i ctspll6 v cc = 5.0 v, internal frequency : 24 mhz, at pll timer mode, external frequency = 4 mhz ? 4 7 ma mb90f347 i ccl v cc = 5.0v internal frequency: 8 khz, at sub operation t a = + 25 c ? 170 360 m a mb90f347 i ccls v cc = 5.0v internal frequency: 8 khz, at sub sleep t a = + 25 c ? 20 50 m a mb90f347 i cct v cc = 5.0v internal frequency: 8 khz, at watch mode t a = + 25 c ? 10 60 m a mb90f347 i cch v cc = 5.0 v, at stop mode, t a = + 25 c ? 7100 m a mb90f347 input capacity c in other than c, av cc , av ss , avrh, avrl, v cc , v ss , ?? 515pf
mb90340 series 55 4. ac characteristics (1) clock timing (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = av ss = 0 v) * : whem selecting the pll clock, the range of clock frequency is limitted. use this product within range as mentioned in relation among external clock frequency and machine clock frequency. parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using an oscillation circuit x0, x1 3 ? 24 mhz when using an external clock* f cl x0a, x1a 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0, x1 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 m s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p whl , p wll x0a 5 15.2 ?m s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock f cpl ? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock t cpl ? 20 122.1 ?m s when using sub clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll clock timing
mb90340 series 56 guaranteed operation range of mb90340 series * : when using the oscillation circuit, the maximum oscillation clock frequency is 16 mhz external clock frequency and machine clock frequency 24 5.5 3.5 1.5 4 power supply voltage v cc (v) guaranteed operation range guaranteed pll operation range 4.0 guaranteed a/d converter operation range machine clock f cp (mhz) 24 4.0 16 12 3 4 12 24 internal clock f cp (mhz) external clock f c (mhz) * x 4 x 3 x 2 x 1 x 1/2 (pll off) 8 8 guaranteed oscillation frequency range 1.5 16 x 6
mb90340 series 57 (2) reset standby input (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) * : oscillation time of oscillator is the time that the amplitude reaches 90 % . in the crystal oscillator, the oscillation time is between several ms and to tens of ms. in far / ceramic oscillators, the oscillation time is between hundreds of m s to several ms. with an external clock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* + 100 m s ? ns in stop mode, sub clock mode, sub sleep mode and watch mode 100 ?m s in time timer mode t rstl 0.2 v cc 0.2 v cc 100 m s rst x0 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset 0.2 v cc rst t rstl 0.2 v cc under normal operation: in stop mode, sub clock mode, sub sleep mode, watch mode:
mb90340 series 58 (3) power on reset (t a = - 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = av ss = 0.0 v) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v holds ram data if you change the power supply voltage too rapidly, a power on reset may occur. we recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. we recommend a rise of 50 mv/ms maximum.
mb90340 series 59 (4) bus timing (read) (t a = C40 c to +85 c, v cc = 4.5 v to 5.5 v, v ss = 0.0 v, machine clock 16 mhz) parameter sym- bol pin condition value unit remarks min max ale pulse width t lhll ale ? t cp /2 - 10 ? ns valid address t ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 - 15 ? ns ale t address valid time t llax ale, ad15 to ad00 t cp /2 - 15 ? ns valid address t rd time t avrl a23 toa16, ad15 to ad00, rd t cp - 15 ? ns valid address t valid data input t avdv a23 to a16, ad15 to ad00 ? 5 t cp /2 - 40 ns rd pulse width t rlrh rd 3 t cp /2 - 20 ? ns rd t valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 - 50 ns rd - t data hold time t rhdx rd , ad15 to ad00 0 ? ns rd t ale - time t rhlh rd , ale t cp /2 - 15 ? ns rd - t address valid time t rhax rd , a23 to a16 t cp /2 - 10 ? ns valid address t clk - time t avch a23 to a16, ad15 to ad00, clk t cp /2 - 15 ? ns rd t clk - time t rlch rd , clk t cp /2 - 15 ? ns ale t rd time t llrl ale, rd t cp /2 - 15 ? ns
mb90340 series 60 a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address vil vih vih vil read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl
mb90340 series 61 (5) bus timing (write) (t a = C40 c to +85 c, v cc = 4.5 v to 5.5 v, v ss = 0.0 v, machine clock 16 mhz) parameter symbol pin condition value unit remarks min max valid address t wr time t avwl a23 to a16, ad15 to ad00, wr ? t cp - 15 ? ns wr pulse width t wlwh wr 3 t cp /2 - 20 ? ns valid data output t wr - time t dvwh ad15 to ad00, wr 3 t cp /2 - 20 ? ns wr - t data hold time t whdx ad15 to ad00, wr 15 ? ns wr - t address valid time t whax a23 to a16, wr t cp /2 - 10 ? ns wr - t ale - time t whlh wr , ale t cp /2 - 15 ? ns wr t clk - time t wlch wr , clk t cp /2 - 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl, wrh) t wlwh 0.8 v 2.4 v t avwl a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx
mb90340 series 62 (6) ready input timing (t a = C40 c to +85 c, v cc = 4.5 v to 5.5 v, v ss = 0.0 v, machine clock 16 mhz) note : if the rdy setup time is insufficient, use the auto-ready function. parameter sym- bol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd/wr rdy when wait is not used. vih vih t ryhh rdy when wait is used. t ryhs vil
mb90340 series 63 (7) hold timing (t a = C40 c to +85 c, v cc = 4.5 v to 5.5 v, v ss = 0.0 v, machine clock 16 mhz) note : there is more than 1 cycle from when hrq reads in until the hak is changed. parameter symbol pin condition value units remarks min max pin floating t hak time t xhal hak ? 30 t cp ns hak - time t pin valid time t hahv hak t cp 2 t cp ns hak each pin high-z t hahv t xhal 2.4v 0.8v 2.4v 2.4v 0.8v 0.8v
mb90340 series 64 (8) uart0/1/2/3/4 (t a = - 40 c to + 105 c, v cc = 4.5 v to 5.5 v, v ss = 0 v) * : refer to (1) clock timing rating for t cp (internal operating clock cycle time). notes : ac characteristic in clk synchronized mode. c l is load capacity value of pins when testing. t cp is the machine cycle (unit : ns) parameter symbol pin condition value unit remarks min max serial clock cycle time t scyc sck0 to sck4 internal clock operation output pins are c l = 80 pf + 1 ttl. 8 t cp * ? ns sck ? sot delay time t slov sck0 to sck4, sot0 to sot4 - 80 + 80 ns valid sin ? sck - t ivsh sck0 to sck4, sin0 to sin4 100 ? ns sck - ? valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns serial clock h pulse width t shsl sck0 to sck4 external clock operation output pins are c l = 80 pf + 1 ttl. 4 t cp * ? ns serial clock l pulse width t slsh sck0 to sck4 4 t cp * ? ns sck ? sot delay time t slov sck0 to sck4, sot0 to sot4 ? 150 ns valid sin ? sck - t ivsh sck0 to sck4, sin0 to sin4 60 ? ns sck - ? valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns internal shift clock mode sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin vil vih t ivsh vil vih t shix
mb90340 series 65 (9) trigger input timing (t a = = = = - - - - 40 c to + + + + 105 c, v cc = = = = 4.5 v to 5.5 v, v ss = = = = 0 v) parameter symbol pin condition value unit remarks min max input pulse width t trgh t trgl int0 to int15, int0r to int15r, adtg ? 5 t cp ? ns external shift clock mode sck vih t slsh vil sot 0.8 v 2.4 v t slov sin vil vih t ivsh vil vih t shix vih vil t shsl vil vih t trgh vil vih t trgl int0 to int15, int0r to int15r, adtg
mb90340 series 66 (10) timer related resource input timing (t a = - 40 c to + 105 c, v cc = 4.5 v to 5.5 v, v ss = 0 v) (11) timer related resource output timing (t a = C40 to +105 c, v cc = 4.5 v to 5.5 v, v ss = 0.0 v) parameter symbol pin condition value unit remarks min max input pulse width t tiwh tin0 to tin3 ? 4 t cp ? ns t tiwl in0 to in7 parameter symbol pin condition value unit remarks min max clk - t t out change time t to tot0 to tot3, ppg0 to ppgf ? 30 ? ns vil vih t tiwh vil vih t tiwl tin0 to tin3, in0 to in7 clk 2.4 v 0.8 v 2.4 v t to tot0 to tot3, ppg0 to ppgf
mb90340 series 67 5. a/d converter (t a = - 40 c to + 105 c, 3.0 v avrh - avrl, v cc = av cc = 5.0 v 10 % , v ss = av ss = 0 v) * : when not operating a/d converter, this is the current (v cc = av cc = avrh = 5.0 v) . note : the accuracy gets worse as avrh - avrl becomes smaller. parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero reading voltage v ot an0 to an23 avrl - 1.5 avrl + 0.5 avrl + 2.5 lsb full scale reading voltage v fst an0 to an23 avrh - 3.5 avrh - 1.5 avrh + 0.5 lsb compare time ?? 1.0 ??m s 4.5 v av cc 5.5 v 2.0 4.0 v av cc 4.5 v sampling time ?? 0.5 ??m s 4.5 v av cc 5.5 v 1.2 4.0 v av cc 4.5 v analog port input current i ain an0 to an23 - 0.3 ? +0.3 m a analog input voltage range v ain an0 to an23 avrl ? avrh v reference voltage range ? avrh avrl + 2.7 ? av cc v ? avrl 0 ? avrh - 2.7 v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 m a* reference voltage current i r avrh ? 600 900 m a i rh avrh ?? 5 m a* offset between input channels ? an0 to an23 ?? 4lsb
mb90340 series 68 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line ( 00 0000 0000 ? ? 00 0000 0001 ) and full-scale transition line ( 11 1111 1110 ? ? 11 1111 1111 ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. zero reading voltage : input voltage which results in the minimum conversion value. full scale reading voltage : input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh - avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n - 1) to n.
mb90340 series 69 (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n - 1 n - 2 v ot ( actual measurement value ) {1 lsb (n - 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error non linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t - v nt 1 lsb - 1 lsb [lsb] v fst - v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from 000 h to 001 h . v fst : voltage at which digital output transits from 3fe h to 3ff h .
mb90340 series 70 7. notes on a/d converter section use the device with external circuits of the following output impedance for analog inputs : recommended output impedance of external circuits are : approx. 1.5 k w or lower (4.0 v av cc 5.5 v, sampling period 0.5 m s) if an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. if output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. 8. flash memory program/erase characteristics parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16 bit width) programming time ? 16 3,600 m s except for the over head time of the system programs/erase cycle ? 10,000 ?? cycle c comparator analog input r 4.5 v av cc 5.5 v : r : = 2.52 k w , c : = 10.7 pf 4.0 v av cc 4.5 v : r : = 13.6 k w , c : = 10.7 pf ? analog input circuit model note : use the values in the figure only as a guideline.
mb90340 series 71 n ordering information (continued) part number package remarks mb90f342pf 100-pin plastic qfp (fpt-100p-m06) mb90f342spf mb90f342cpf mb90f342cspf mb90f342pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f342spfv mb90f342cpfv mb90f342cspfv mb90f343pf 100-pin plastic qfp (fpt-100p-m06) mb90f343spf mb90f343cpf mb90f343cspf mb90f343pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f343spfv mb90f343cpfv mb90f343cspfv mb90f345pf 100-pin plastic qfp (fpt-100p-m06) mb90f345spf mb90f345cpf mb90f345cspf mb90f345pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f345spfv mb90f345cpfv mb90f345cspfv mb90f346pf 100-pin plastic qfp (fpt-100p-m06) mb90f346spf mb90f346cpf mb90f346cspf mb90f346pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f346spfv mb90f346cpfv mb90f346cspfv
mb90340 series 72 (continued) part number package remarks mb90f347pf 100-pin plastic qfp (fpt-100p-m06) mb90f347spf mb90f347cpf mb90f347cspf mb90f347pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f347spfv mb90f347cpfv mb90f347cspfv mb90f349pf 100-pin plastic qfp (fpt-100p-m06) mb90f349spf mb90f349cpf mb90f349cspf mb90f349pfv 100-pin plastic lqfp (fpt-100p-m05) mb90f349spfv mb90f349cpfv mb90f349cspfv mb90341pf 100-pin plastic qfp (fpt-100p-m06) mb90341spf mb90341cpf mb90341cspf mb90341pfv 100-pin plastic lqfp (fpt-100p-m05) mb90341spfv mb90341cpfv mb90341cspfv mb90342pf 100-pin plastic qfp (fpt-100p-m06) mb90342spf mb90342cpf mb90342cspf mb90342pfv 100-pin plastic lqfp (fpt-100p-m05) mb90342spfv mb90342cpfv mb90342cspfv
mb90340 series 73 (continued) part number package remarks mb90346pf 100-pin plastic qfp (fpt-100p-m06) mb90346spf mb90346cpf mb90346cspf mb90346pfv 100-pin plastic lqfp (fpt-100p-m05) mb90346spfv mb90346cpfv mb90346cspfv mb90347pf 100-pin plastic qfp (fpt-100p-m06) mb90347spf MB90347Cpf MB90347Cspf mb90347pfv 100-pin plastic lqfp (fpt-100p-m05) mb90347spfv MB90347Cpfv MB90347Cspfv mb90348pf 100-pin plastic qfp (fpt-100p-m06) mb90348spf mb90348cpf mb90348cspf mb90348pfv 100-pin plastic lqfp (fpt-100p-m05) mb90348spfv mb90348cpfv mb90348cspfv mb90349pf 100-pin plastic qfp (fpt-100p-m06) mb90349spf mb90349cpf mb90349cspf mb90349pfv 100-pin plastic lqfp (fpt-100p-m05) mb90349spfv mb90349cpfv mb90349cspfv mb90v340 299-pin ceramic pga (pga-299c-a01) for evaluation
mb90340 series 74 n package dimensions (continued) 100-pin plastic qfp (fpt-100p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness including plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 C0.20 +.014 C.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * *
mb90340 series 75 (continued) 100-pin plastic lqfp (fpt-100p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f100007s-c-4-6 14.000.10(.551.004)sq 16.000.20(.630.008)sq 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.0057.0022) 0.08(.003) "a" index .059 C.004 +.008 C0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) details of "a" part (stand off) *
mb 90340 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f030 5 ? fujitsu limited printed in japan

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